Implementation based on the paper Convolutional Differentiable Logic Gate Networks
Python Version: 3.9.21
FPGA: Efinix Trion 120
UART RX: GPIOT_RXN28
UART TX: GPIOT_RXP28
Clock: GPIOR_188 (PLL_BR2)
Clock frequency: 5MHz
Constraint: 200ns
b1shtream/conv_differentiable_logic_gate_networks
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