Show & Tell: Experimental Open-Source NPU Array V1 (Roadmapping 1-bit/XNOR accelerators)

[n57d30top]

Hi everyone,

I recently decided to open-source an experimental spatial compute architecture I've been working on: the Graph-Assist NPU Array V1.

Instead of building another bloated deep-learning chip that tries to do every math operation possible, I stripped it down. The V1 baseline currently operates on a strict, bare-metal 3-opcode primitive set (ADD/MUL/MAC) for dense inference.

The crucial roadmap step (V1.1) is introducing a parallel XNOR+POPCOUNT bitwise path to natively accelerate 1-bit / ternary network matrix multiplications in hardware without breaking the dense routing core.

Repository: https://github.com/n57d30top/graph-assist-npu-array-v1-direct-add-commit-add-hi-tap

What’s in the V1 open-source release:

Clean RTL for the spatial array
Verilator smoke test environments
Complete SymbiYosys formal verification harness
Full physical design routing metadata & timing reports via OpenLane to track realistic congestion constraints.
I am sharing the V1 baseline now because I’d love to get architectural roasts and practical feedback from the low-level compute community before I start wiring up the complex 1-bit logic paths.

Let me know what you think about the routing strategy and topology!